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drives two 13x16 matrix heads head temperature sensing power up system electrical nozzle check 8 bit a/d 5 bit d/a 4kv esd protected outputs description l6452 is a device designed to drive two 13x16 matrix ink jet printheads in printer applications. the output stage is able to source simultaneously 400 ma on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. on the address lines (rows), the load is only capacitive (mos fet driv- ing capability). the driver can control two print- heads, but only one is active at a time. the ad- dress scanning counter is included and can be disabled to allow a different scanning scheme. in order to avoid output activation during the sup- ply transient, an internal power-up system is im- plemented. as supporting function, l6452 is capable of sens- ing the head silicon temperature and to electri- cally check each nozzle. the device is also integrating a thermal protec- tion. march 1999 ? print head driver print head temperature control power & logical supplies control lines a/d & print head temperature control lines analog inputs print head a print head b d97in523 13 address lines channel b 16 power lines 13 address lines channel a figure 1. block diagram pqfp100 l6452 dual 13x16 matrix head ink jet driver 1/16
pin functions pin # name function 1 crlatch a rising edge latches the information present into the control register 2, 5, 6, 8, 9, 11, 12, 14, 16, 18, 19, 21, 22, 24, 25, 28 output 15...0 high side dmos outputs. to be active, short pulse and/or long pulse and nozzle check enable must have a low level 3, 7, 10, 13, 17, 20, 23, 26 vc outputs power supply 4, 15, 27, 51, 79, 92 gnd logic and power ground 29 latch clear a high level resets all bit in the latch 1 2 3 5 6 4 7 8 9 10 36 11 37 38 39 40 41 95 94 93 92 90 91 89 88 87 86 85 70 69 68 66 65 67 75 74 73 71 72 output13 output14 powgnd output15 crlatch v c output10 v c output11 v c output12 _reset conv_start adck ncout addata ch0_buf analognd adcgnd v a vref ch5 rxa rxb rext cs_gnd v a v dd vstep-up stepup_bo stepup_gnd clkcs0 _ench hsa4 hsa5 hsa6 hsa8 hsa9 hsa7 enlc gnd hsa1 hsa3 hsa2 d97in489b 96 vxa 97 vxb 98 _onenable 99 crclock 100 crdata latch_data sdi sdc long_pulse short_pulse 31 32 33 34 35 64 63 61 60 62 hsa10 hsa11 hsa13 v r hsa12 12 13 14 15 16 output7 powgnd output8 output9 v c 17 18 19 20 v c output5 output6 v c 21 22 23 24 25 output1 output2 v c output4 output3 59 57 56 58 hsb13 hsb11 hsb10 hsb12 hsb9 hsb8 hsb6 hsb5 hsb7 45 46 47 48 49 50 84 83 81 82 ch4 ch3 ch1 ch2 rescs1 upc52 chsel s3 42 43 44 26 27 28 29 30 ncen latch_clear output0 v c powgnd 55 54 52 51 53 hsb4 hsb3 hsb1 gnd hsb2 80 79 78 76 77 pin connection (top view) l6452 2/16
pin # name function 30 ncen a high level enables the internal current sources and disables all dmos outputs. to be active, the internal current sources must have their corrsponding bit set in the 16 bit latch and long pulse must be set to low level. a low level enables the internal hsa/b short circuit detection 31 latch data a rising edge latches the 16 bit stored in the shift register in the 16 bit latch 32 sdi serial data input of the shift register 33 sdc the data bit presented to the serial data input pin is stored into the register on the rising edge of this pin 34 long pulse a low level activates all outputs having their coresponding bit in the 16 bit latch set (this pin has an internal pull-up resistor) 35 short pulse a low level activates all outputs having their coresponding bit in the 16 bit latch reset (this pin has an internal pull-up resistor) 36 _reset a low level disables all functions and clears all registers 37 convstart a high level enables the a/d to start the new conversion 38 adck a/d clock signal; the addata signal are valid on the falling edge of this pin 39 ncout if nozzle check enable is high this output provides a high level when the open load is detected on the output. if nozzle check enable is low this output provides a high level when a short circuit is detected on hsa/b output 40 ch0_buf analog output signal (ch0 buffered) 41 addata a/d serial data output 42 analoggnd analog ground connection 43 adcgnd ground of internal adc 44, 90 va power supply 45 vref reference voltage generator 46 to 50 ch5..ch1 a/d input signals 52 to 64 hsb1..hsb13 head selector address output channel b 65 vr head select power supply 66 to 78 hsa13..hsa1 head selector address output channel a 80 enlc a high level enables the counter and the internal decoder will activate of the hsx outputs according to the counters outputs. signal s0 becomes clock counter and s1 becomes reset counter 81 chsel a low level enables channel a and a high level enables channel b 82 s3 decoder input signals when enable counter is low 83 upc/ s2 a high level enables the internal counter to up counting. a low level enables down counting 84 resc/s1 a low level resets the internal counter 85 _ench a low level enables the selected channel (this input has an internal pull up resistor) 86 clkc/s0 a high level clocks the internal counter 87 step up gnd ground of step up block 88 step up boost boost voltage 89 vstep up driving voltage of power dmos stage 91 vdd 5v logic supply 93 rext an external resistor connected versus ground fixes the internal current source value 94, 95 rxb, rxa current source outputs 96, 97 vxa, vxb rxa, rxb voltage after an optional external filter 98 _onenable a low level enables the current source generator according the _a/b and on/_off control register bit 99 crclock data on pin crdata are stored into the register on the rising edge of this pin 100 crdata control register serial data input pin functions (continued) l6452 3/16
16 bit serial input & parallel output 16 bit latch 16 power output stages output 0 output 1 output 2 output 3 output 4 output 5 output 6 output 7 output 8 output 9 output 10 output 11 output 12 output 13 output 14 output 15 nozzle check output serial data input serial data clock latch clear latch data nozzle check enable * long pulse * short pulse selector 4 to 13 lines decoder 13 mos drivers channel a hsa 1 enable internal counter sel 3 up counting/sel 2 *reset counter/sel 1 clock counter/sel 0 hsa 2 hsa 3 hsa 4 hsa 5 hsa 6 hsa 7 hsa 8 hsa 9 hsa 10 hsa 11 hsa 12 hsa 13 13 mos drivers channel b hsb 1 hsb 2 hsb 3 hsb 4 hsb 5 hsb 6 hsb 7 hsb 8 hsb 9 hsb 10 hsb 11 hsb 12 hsb 13 c0 c1 c2 c3 0 to 13 up/down counter *select channel *enable channel d97in524 figure 2. block diagram: nozzle activation part. l6452 4/16
nozzle check enable trigger *long pulse * short pulse data bit 15 data bit 1 data bit 0 1 0 nozzle check output output 15 output 1 output 0 power supply d97in525 10ma from 16 bit data latch figure 3. block diagram: power line output stage. l6452 5/16
absolute maximum ratings symbol parameter value unit v c power line supply voltage 14 v v r address line supply voltage 14 v v a analog supply voltage 14 v v dd logic supply voltage 6 v v step_up driving voltage of power dmos stage 28 v v in logic input voltage range -0.3 to v dd +0.3 v i out output continuous current 0.5 a t j junction temperature 150 c t amb operating temperature range 0 to 70 c t stg storage temperature range -55 to 150 c dc electrical characteristics (t j = 25 c) symbol parameter test condition min. typ. max. unit v c power line supply voltage * 10.5 ** 11.5 12.5 v v r address line supply voltage * 10.5 11.5 12.5 v v a analog supply voltage * 10.5 11.5 12.5 v v dd logic supply voltage 4.5 5 5.5 v i cs v c sleep supply current onenable = 1 reset = 0 1ma i rs v r sleep supply current 0.3 ma i as v a sleep supply current 3 ma i c vc supply current 1.5 ma i r vr supply current 0.6 ma i a va supply current i rext = 3ma 13 ma i dd v dd supply current sleep or normal condition 5 ma v ref reference voltage t amb = 5 to 55c 4.85 5 5.15 v i refext reference current (external) 7 ma i css programmed constant current i ccs = v ref 2r ext 4 12 13.5 ma d i css /i css constant current regulation v a =11v t amb = 5 to 55c 0.33 % v ampout output voltage of integrated amplifier e *** va-1 v v cm operating input voltage at pins vxa and vxb v ref = 5v g1=1.2 g2=3 7 v g1 amp. a1 voltage gain 1.188 1.2 1.212 g2 amp.a2 voltage gain 2.95 3.02 3.10 v step-up driving voltage of power dmos vc +11 v * the three supply voltage are independent inside the specified value; ** the min value for vc power line could be decreased up to 9v (under evaluation); *** e = 2 v step a/d converter v a/d in a/d input voltage selected channel: ch1toch5 selected ch=ch0 0 e *** vref vref v v i exch a/d input current input ch1 to ch5 channel selected or not 1 m a offset voltage generation / dac v offset offset voltage v ref = 5v 2.5 + e*** 7.34 v v step voltage increment (1lsb) v ref = 5v 156 mv k dac voffset/vref any step n>=4 3% l6452 6/16
symbol parameter test condition min. typ. max. unit a/d converter timings t cscks conv. start set up time 200 ns t csckh conv. start hold time 200 ns t ckout falling edge of clock to data out valid delay c load 20pf 200 ns t csz convstart falling edge to output in hi-z delay 200 ns f adck clock frequency 250 khz t cslow conv. start low level time 5.6 m s t acq th theoretical acquisition time f adck = 250 khz 32.4 m s t acq pr real acquisition time f adck = 250 khz 36 m s digital interface input v inp schmitt trigger positive-going threshold 2/3v dd v v inm schmitt trigger negative-going threshold 1/3v dd v v hys scmitt trigger hysteresis 0.1 0.3 1 v i in input current (vin=0; vdd=5)* 50 150 300 m a * this applies to input pins having an internal pull-up (enable_channel, long_pulse, short_pulse) cr latch timings t ls latch set up time 100 ns t lhigh latch high time 100 ns t lconv latch data valid to a/d input valid delay selected channel: ch1..ch5 ch0 4 7 m s m s nb: the control register (driving signals crdata, crclock) is accessed with the same timing specifications as the data 16 bit shift register (signals serial data, serial clock) shift register and latch timing t a set up time 50 ns t b hold time 50 ns t c serial clock low time 50 ns t d serial clock high time 50 ns t e serial clock period 150 ns t f latch set up time 100 ns t g latch data high time 100 ns t set long pulse set_up time with respect to ncen 160 ns t hold long pulse hold time with respect to ncen 0ns outputs electrical characteristics i out output current (outputs 0..15) dc=33%; preheating dc=66% 400 ma r ds (on) on resistance t j = 25c 1.3 w t on turn on time (tdelay + trise) from 50% long pulse to 90% power output rising edge load = 30 ohm in parallel with 1.5nf 160 ns t off toff delay time from 50% long pulse to 90% power output falling edge load = 30 ohm in parallel with 1.5nf 100 ns dc electrical characteristics (t j = 25 c) l6452 7/16
symbol parameter test condition min. typ. max. unit head address selector output t h up counting, reset counter, select channel, clock counter and enable internal counter set-up time with respect to enable channel 150 ns t k up counting, reset counter, select channel, clock counter and enable internal counter hold time with respect to enable channel 50 ns t j up counting with respect to clock counter hold time 200 ns t i up counting with respect to clock counter set_up time 100 ns t m enable input to active output delay time 100 ns t n clock to active output delay time 150 ns t o disable input to inactive output delay time 100 ns f clk-counter counter clock frequency 1 mhz clk dc clock duty cycle 10 90 % t on/off turn on/off time from 50% clock counter or selector signal to 90% of the address output variation load: see fig. 10 325 ns counter truth table enable internal counter = 1 up counting = 1 reset counter = 1 clock counter c3 c2 c1 c0 00000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1000 0000 dc electrical characteristics (t j = 25 c) l6452 8/16
enable internal counter = 1 up counting = 0 reset counter = 1 clock counter c3 c2 c1 c0 00000 1000 1010 1110 1111 1101 1100 0100 0101 0111 0110 0010 0011 0001 0000 decoder truth table outputs (hs) active c3 c2 c1 c0 all inactive 0000 10001 20011 30010 40110 50111 60101 70100 81100 91101 101111 111110 121010 131000 all inactive 1001 all inactive 1011 this table is valid for both channel a and channel b and when enable channel is set to low level. counter truth table (continued) l6452 9/16
print head temperature control part introduction for quality printing, it is necessary to know and control the temperature of the printhead. thus, the latter has a built - in aluminium resistor, whose value changes slightly with the tempera- ture. the temperature determination is done by injecting a constant current in the resistor, and measuring the voltage drop across it. since high - end printers have two heads, it must also be pos- sible to switch quikly the measurement process from one to the other. the function is foreseen to be integrated into the head driver, and is de- scribed hereafter. print head block diagram (fig. 4) at first we have a constant current source, which can be disabled by an external pin (onenable) or by a control register, described later. the value of the current can be programmed by an external resistor, and is given by: i ccs = v ref 4 2 r ext this current is injected either into the aluminium resistor of the head a (ralu. a) or b (ralu. b), de- pending of the switch sw3. the alu. resistors are grounded, and the voltage at their << hot >> side (vx) is re-entered via the pins vxa and vxb. us- ing separate pins from rxa and rxb permits to be more flexible, and a filter can eventually be added as shown in the drawing. the voltage vx is amplified by a1 and a2, and then converted in a digital value. to be compat- ible with the input range of the a/d converter, it is necessary to subtract an offset voltage voffset from vx. moreover, as the initial value of the alu. resistor is very unprecise. voffset must be adjust- able; this is done by means of a 5 bit - d/a con- verter, giving 32 different values. finally, the volt- age at the input of the a/d converter is: v ch0 = g1 g2 v x - g2 v offset or v ch0 = g1 g2 ralu i ccs - g2 v offset ; v offset = v ref /2 + n v ref /32 n = 0, 1, ...31 the reference voltage generator (v ref ) is inte- grated, and used for the current source and both the a/d and d/a converters. in this way, the sys- tem performance is independent from the preci- sion of v ref ; this one should, however, be stable. vref is also available on pin #45, and can be used for low consumption purposes. (the exter- nal sinked current has to be a dc current) the system is under control of a 10 bit register, cr. cr is accessed serially and has a transpar- ent latch, which can be used or not (by trying the latch signal cr latch to v cc ). ref volt vref + g1 a1 g2 a vref/2 vref out va d/a 5 bit a/b on/off da4 da3 da2 da1 da0 s2 s1 s0 d vref control register latch 10 bit shift reg. 10 bit crlatch crclock crdata a b d c vref a2 vx sw1 sw2 sw3 ch0 + - ch1 ch2 ch3 ch4 ch5 addata adck conv start a/d inputs ch0_buf rext onenable rxa, rxb vxa, vxb ralu b ralu a analog gnd note; the analog ground is separated from the digital ground of the remaining part of the driver d97in533b high-side constant current source voffset figure 4. print head block diagram l6452 10/16
a/b on/off da4 da3 da2 da1 da0 s2 s1 s0 d/a inputs for offset compensation d97in534a cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 channel selection a/d input shift direction selection of resistor a (a/b = 0) or b (a/b = 0) for temperature measurement switches the current source on or off; linked with onenable input pin on/off onenable action 0 1 0 1 1 1 0 0 off off off on s2 selected channel ch0 buf 0 0 0 0 0 (internal) 1 (external) 2 (external) 3 (external) a b b b one internal channel (vx measurement) five uncommitted, genral-purpose external channels s1 0 0 1 1 s0 0 1 0 1 1 1 0 0 0 1 4 (external) 5 (external) b b c d da0 = lsb da4 = msb positive logic 110 6 111 7 figure 5. control register details. t lconv t lhigh t ls convstart crlatch crclock crdata d97in535 da0 s2 s1 s0 figure 6. cr latch timings t csx t cscks adck addata d97in536 65 4 2 731 0 high impedance convstart high impedance t csckh t ckout figure 7. a/d converter timings l6452 11/16
+ - internal reference 1 0 ncem v power v logic nozzle check output from the common connection of analog multiplexers hsa/b short circuit detection d97in527 figure 9. trigger of nozzle check signal 50% 50% 90% 90% 10% 10% t f t r long pulse or short pulse power output d97in526 t d t d figure 8. power output timing l6452 12/16
t o t k t i t j t h t m t n output 1 :13 hsa or hsb) enable channel clock counter enable internal counter select channel reset counter up counting d97in529a figure 11. mode counter 50% 50% 90% 90% 10% 10% t f t r sel 0 to 3 address output measured at point a d97in528a t d t d hs output 200 w a 250pf clock signal counter selector signal figure 10. address output timing l6452 13/16
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 serial data serial clock latch data long pulse short pulse output * output ** * the corresponding data bit is set ** the corresponding data bit is reset d97in531 figure 13. sequence of shift register data loading t o t k t h t m t n output 1 :13 hsa or hsb) enable channel enable internal counter select channel sel 0:3 d97in530 figure 12. mode sel 0:3 t c t g latch data serial clock serial data d97in532 t a t b t d t e t f figure 14. latch timing l6452 14/16
pqfp100 dim. mm inch min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.22 0.38 0.0087 0.015 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.903 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.85 0.742 e 0.65 0.026 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.35 0.486 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) outline and mechanical data l6452 15/16
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com l6452 16/16

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